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USBLC6-4
Very low capacitance ESD protection
Features
4 data lines protection Protects VBUS Very low capacitance: 3 pF typ. SOT23-6L package RoHS compliant

SOT23-6L
Benefits

Very low capacitance between lines to GND for optimized data integrity and speed Low PCB space consumption, 9 mm maximum foot print Enhanced ESD protection. IEC 61000-4-2 level 4 compliance guaranteed at device level, hence greater immunity at system level ESD protection of VBUS. Allows ESD current flowing to Ground when ESD event occurs on data line High reliability offered by monolithic integration Low leakage current for longer operation of battery powered devices
Applications

USB 2.0 ports up to 480 Mb/s (high speed) Backwards compatible with USB 1.1 low and full speed Ethernet port: 10/100 Mb/s SIM card protection Video line protection Portable electronics
Description
The USBLC6-4SC6 is a monolithic application specific device dedicated to ESD protection of high speed interfaces, such as USB 2.0, Ethernet links and video lines. Its very low line capacitance secures a high level of signal integrity without compromising in protecting sensitive chips against the most stringent characterized ESD strikes. Figure 1. Functional diagram
I/O1
1 1 6
Fast response time Consistent D+ / D- signal balance: - Best capacitance matching tolerance I/O to GND = 0.015 pF - Compliant with USB 2.0 requirements < 1 pF
Complies with the following standards
IEC 61000-4-2 level 4: - 15 kV (air discharge) - 8 kV (contact discharge)
I/O4
GND
2
5
VBUS
I/O2
3
4
I/O3
February 2008
Rev 3
1/13
www.st.com 13
Characteristics
USBLC6-4
1
Characteristics
Table 1.
Symbol
Absolute ratings
Parameter IEC 61000-4-2 air discharge IEC 61000-4-2 contact discharge MIL STD883C-Method 3015-6 Value 15 15 25 -55 to +150 -40 to +125 260 Unit
VPP Tstg Tj TL
Peak pulse voltage Storage temperature range
kV C C C
Operating junction temperature range Lead solder temperature (10 seconds duration)
Table 2.
Symbol VRM IRM VBR VF
Electrical characteristics (Tamb = 25 C)
Value Parameter Reverse stand-off voltage Leakage current Breakdown voltage between VBUS and GND Forward voltage VRM = 5 V IR = 1 mA IF = 10 mA IPP = 1 A, 8/20 s Any I/O pin to GND 6 0.86 12 17 3 0.015 Capacitance between I/O VR = 1.65 V 1.85 0.04 2.7 pF 4 pF 10 Test Conditions Min. Typ. Max. 5 150 V nA V V V V Unit
VCL
Clamping voltage IPP = 5 A, 8/20 s Any I/O pin to GND Capacitance between I/O and GND VR = 1.65 V
Ci/o-GND Ci/o-GND Ci/o-i/o Ci/o-i/o
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USBLC6-4
Characteristics
Figure 2.
C(pF)
5.0 4.5 4.0 3.5
Capacitance versus voltage (typical values)
Figure 3.
C(pF)
5.0
Line capacitance versus frequency (typical values)
VOSC=30mVRMS Tj=25C VCC=0V
F=1MHz VOSC=30mVRMS Tj=25C
4.5 4.0 3.5
CO=I/O-GND
VCC=1.65V
3.0 2.5
Cj=I/O-I/O
3.0 2.5 2.0 1.5 1.0
2.0 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Data line voltage (V)
0.5 0.0 1 10
F(MHz)
100 1000
Figure 4.
Relative variation of leakage current versus junction temperature (typical values)
VBUS=5V
Figure 5.
Frequency response
IRM[Tj] / IRM[Tj=25C]
100
0.00
S21(dB)
-5.00
10
-10.00
-15.00
Tj(C)
1 25 50 75 100 125
F(Hz)
-20.00 100.0k 1.0M 10.0M 100.0M 1.0G
3/13
Technical information
USBLC6-4
2
2.1
Technical information
Surge protection
The USBLC6-4SC6 is particularly optimized to provide surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follows: VCL+ = VTRANSIL + VF for positive surges VCL- = - VF for negative surges with: VF = VT + Rd.Ip (VF forward drop voltage, VT forward drop threshold voltage
Calculation example
We assume that the value of the dynamic resistance of the clamping diode is typically: Rd = 0.5 and VT = 1.1 V. For an IEC 61000-4-2 surge level 4 (Contact Discharge: Vg = 8 kV, Rg = 330 ), VBUS = +5 V, and if in a first approximation, we assume that: Ip = Vg / Rg = 24 A. So, we find: VCL+ = +31.2 V VCL- = -13.1 V Note: The calculations do not take into account phenomena due to parasitic inductances.
2.2
Surge protection application example
If we consider that the connections from the pin VBUS to VCC, from from I/O to data line and from GND to PCB GND plane are implemented as racks 10 mm long and 0.5 mm large, we can assume that the parasitic inductances LVBUS LI/0 and LGND of these tracks are about 6 nH. So, when an IEC 61000-4-2 surge occurs, due to the rise time of this spike (tr = 1 ns), the voltage VCL has an extra value equal to LI/0*dI/dt, + LGND*dI/dt The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns The overvoltage due to the parasitic inductances is: LI/0*dI/dt, = LGND*dI/dt = 6 x 24 = 144 V By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be: VCL+ = +31.2 + 144 + 144 = 319.2 V VCL- = -13.1 - 144 -144 = -301.1 V We can significantly reduce this phenomena with simple layout optimization. It is for this reason that some recommendations have to be followed (see 2.3: How to ensure good ESD protection).
4/13
USBLC6-4 Figure 6.
Technical information ESD behavior: parasitic phenomena due to unsuitable layout
ESD sur ge on data line VBUS Data line
L I/O L I/O di dt L VBUS VCC pin VF VTRANSIL I/O pin VCL VTRANSIL + VF t t r = 1 ns GND pin t r = 1 ns L GND L GND di dt - VF t L I/O di + L GND di dt dt VCL+
Positive Sur ge
VCL + = VTRANSIL + VF + L I/O di + L GND di dt dt VCL- = -VF - L I/O di - L GND di dt dt V TRANSIL = VBR + Rd.Ip
sur ge > 0 sur ge > 0
-L I/O di - L GND di dt dt
Negative Sur ge
VCL-
2.3
How to ensure good ESD protection
While the USBLC6-4SC6 provides high immunity to ESD surge, efficient protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from data lines to I/O pins, from VCC to the VBUS pin and from GND plane to GND pin must be as short as possible to avoid overvoltages due to parasitic phenomena (see Figure 7 and Figure 8 for layout considerations)
Figure 7.
ESD behavior: optimized layout and Figure 8. addition of a capacitance of 100 nF
ESD behavior: measurement conditions (with coupling capacitance)
ESD SURGE TEST BOARD
Unsuitable layout
IN
OUT
USBLC6-4SC6
Vbus
Optimized layout
5/13
Technical information
USBLC6-4
Figure 9.
Remaining voltage after the Figure 10. Remaining voltage after the USBLC6-4SC6 during positive ESD USBLC6-4SC6 during negative ESD surge surge
Note:
The measurements have been done with the USBLC6-4SC6 in open circuit.
Important:
A good precaution to take is to put the protection device as close as possible to the disturbance source (generally the connector).
2.4
2.4.1
Crosstalk behavior
Crosstalk phenomenon
Figure 11. Crosstalk phenomenon
RG1 Line 1 1 VG1 + 12VG2
VG1 RG2 Line 2
RL1
VG2
RL2
2VG2 + 21VG1
DRIVERS
RECEIVERS
The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (12 or 21) increases when the gap across lines decreases, particularly in silicon dice. In the above example the expected signal on load RL2 is 2VG2, in fact the real voltage at this point has got an extra value 21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few k).
6/13
USBLC6-4 Figure 12. Analog crosstalk measurements
TEST BOARD NETWORK ANALYSER PORT 1
USBLC6-4SC6
Technical information
NETWORK ANALYSER PORT 2 Vbus
Figure 12. shows the measurement circuit for the analog application. In usual frequency range of analog signals (up to 240 MHz) the effect on disturbed line is less than -55 db ( see Figure 13.). Figure 13. Analog crosstalk results
0.00 dB - 30.00
- 60.00
- 90.00
F (Hz)
- 120.00 100.0k
1.0M
10.0M
f/Hz
100.0M
1.0G
As the USBLC6-4SC6 is designed to protect high speed data lines, it must ensure a good transmission of operating signals. The frequency response (Figure 5.) gives attenuation information and shows that the USBLC6-4SC6 is well suitable for data line transmission up to 480 Mbit/s while it works as a filter for undesirable signals like GSM (900 MHz) frequencies, for instance.
7/13
Technical information
USBLC6-4
2.5
Application examples
Figure 14. USB 2.0 port application diagram using USBLC6-4SC6
+ 3.3V DEVICEUPSTREAM RPU TRANSCEIVER
SW2
VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND TX LS/FS + TX LS/FS -
+ 5V
USB connector
Protecting Bus Switch
HUBDOWNSTREAM TRANSCEIVER
SW1
VBUS D+
DRS RS RPD
USBLC6-2SC6
VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS -
GND
RS RS RPD
GND TX LS/FS + TX LS/FS -
+ 3.3V DEVICEUPSTREAM RPU TRANSCEIVER
SW2
VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND TX LS/FS + TX LS/FS -
SW1
USB connector
VBUS D+
DRS RS
USBLC6-2P6
RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS -
GND
RS
GND TX LS/FS +
USBLC6-4SC6
RPD
RS RPD
TX LS/FS -
Mode Low Speed LS Full Speed FS High Speed HS
SW1 Open Closed
SW2 Closed Open
Closed then open Open
Figure 15. T1/E1/Ethernet protection
Tx
SMP75-8
USBLC6-4SC6
+VCC 100nF
DATA TRANSCEIVER
Rx
SMP75-8
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USBLC6-4
Technical information
2.6
PSPICE model
Figure 16. shows the PSPICE model of one USBLC6-4SC6 cell. In this model, the diodes are defined by the PSPICE parameters given in Figure 17.
Figure 16. PSPICE model
MODEL = Dlow LIO io1 MODEL = Dlow RIO
MODEL = Dhigh RIO MODEL = Dhigh LIO io4
LGND GND
RGND
MODEL = Dzener
RIO
LIO VBUS
MODEL = Dlow LIO io2 MODEL = Dlow RIO
MODEL = Dhigh RIO MODEL = Dhigh LIO io3
Note:
This simulation model is available only for an ambient temperature of 27 C. Figure 18. USBLC6-4SC6 PCB layout considerations
Figure 17. PSPICE parameters
Dlow BV CJ0 IBV IKF IS ISR N M RS VJ TT 50 2.4p 1m 0.038 55.2p 100p 1.62 0.3333 0.38 0.6 0.1u
Dhigh 50 2.4p 1m 0.018 2.27f 100p 1.13 0.3333 0.63 0.6 0.1u
Dzener 7.3 20p 1m 2.42 3.21p 100p 1.24 0.3333 0.42 0.6 0.1u LIO RIO LGND RGND 710p 100m 430p 50m
D+1 D-1 GND D+2 D-2
1
VBUS CBUS = 100nF
USBLC6-4SC6
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Ordering information scheme
USBLC6-4
3
Ordering information scheme
Figure 19. Ordering information scheme
USB
Product Designation Low capacitance Breakdown Voltage 6 = 6 Volts Number of lines protected 4 = 4 lines Package SC6 = SOT23-6L
LC
6-4
SC6
10/13
USBLC6-4
Package information
4
Package information
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Table 3. SOT23-6L dimensions
Dimensions
A
E
REF.
Millimeters Min. Typ. Max. Min.
Inches Typ. Max. 0.057 0.004 0.051 0.02 0.008 0.120 0.069 0.037
A
e b e
D
0.90 0 0.90 0.35 0.09 2.80 1.50 0.95 2.60 0.10 0
1.45 0.035 0.10 0
A1 A2 b C
A2
1.30 0.035 0.50 0.014 0.20 0.004 3.05 0.110 1.75 0.059
D E e
c
A1
L
H
H L
3.00 0.102 0.60 0.004 10 0
0.118 0.024 10
Figure 20. SOT23-6L footprint (mm)
0.60
Figure 21. SOT23-6L marking
1.20
e3
3.50
2.30
0.95
1.10
xxx z y ww
e3: ECOPACK (Leadfree) XXX: Marking Z: Manufacturing location Y: Year WW: week
11/13
Ordering information
USBLC6-4
5
Ordering information
Table 4. Ordering information
Marking UL46 Package SOT23-6L Weight 16.7 mg Base qty 3000 Delivery mode Tape and reel
Ordering code USBLC6-4SC6
6
Revision history
Table 5.
Date 10-Dec-2004 28-Feb-2005
Document revision history
Revision 1 2 First issue. Minor layout update. No content change. Updated operating junction temperature range in absolute ratings, page 2. Updated Section 2: Technical information. Updated marking illustration Figure 21. Reformatted to current standard. Description of changes
04-Feb-2008
3
12/13
USBLC6-4
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